1. Field of the Invention
The present invention relates to a pin card.
2. Description of the Related Art
A semiconductor test apparatus (which will be referred to simply as the “test apparatus” hereafter) is used to test whether or not a semiconductor device operates normally or to identify defective parts. A typical test apparatus performs an AC test operation and a DC test operation.
In the AC test operation, a test pattern is generated by a pattern generator and a timing generator, and a driver supplies the test pattern thus generated to a device under test (DUT). Upon receiving the pattern signal, the DUT performs predetermined signal processing, and outputs an output signal to the test apparatus. By means of a timing comparator, the test apparatus judges the signal level received from the DUT. By comparing the judgment result with an expected value, the test apparatus judges the quality of the functions of the DUT.
In the DC test operation, a DC test unit supplies a DC voltage or a current signal to the DUT, and the test apparatus tests the DC characteristics such as the input/output impedance of the DUT, the leak current thereof, and so forth.
In many cases, a driver, a timing comparator, and a PMU configured to perform a DC test operation are arranged on a board which is referred to as a pin card (pin electronics card), a digital module, or an interface card, and which is configured such that the board can be removed from the main unit of the test apparatus.
FIG. 1 is a diagram which shows a configuration of a typical pin card. FIG. 1 shows only one channel that corresponds to a given device pin. In practice, several hundreds through several thousands of channels are arranged in parallel.
An I/O terminal Pio of a pin card 200 is connected to a corresponding device pin of a DUT 1 via a cable and an unshown device chuck. The pin card 200 includes two switches (relays) SW1 and SW2, in addition to a driver DR, a timing comparator TCP, and a DC test unit PMU. The switches SW1 and SW2 are used to switch the test mode between the AC test mode and the DC test mode.
When the AC test operation is performed, the switch SW1 is turned on and the switch SW2 is turned off. In this state, the driver DR and the timing comparator TCP are connected to the DUT 1, and the DC test unit PMU is disconnected from the DUT 1.
Conversely, when the DC test operation is performed, the switch SW1 is turned off and the switch SW2 is turned on. In this state, the driver DR and the timing comparator TCP are disconnected from the DUT 1, and the DC test unit PMU is connected to the DUT 1.
In a case in which the frequency of the test pattern is higher than several Gbps, a high-frequency signal having a frequency exceeding several GHz passes through the switch SW1. In this case, as such a switch SW1, there is a need to employ a composite semiconductor switch or MEMS (Micro Electro Mechanical Systems) switch which is capable of transmitting such a high-frequency signal.
However, such a composite semiconductor switch has a very low DC breakdown voltage on the order of 0.1 V. Accordingly, such a composite semiconductor switch cannot be used to handle a test pattern including a DC component. Moreover, although such a MEMS switch satisfies the requirements of such high-speed operation and sufficient DC breakdown voltage, such a MEMS switch has a problem of a high cost. Specifically, the cost of such a MEMS switch is almost 100 times that of other switches. As described above, such a mass-production test apparatus includes several hundreds to several thousands of channels. Accordingly, if MEMS switches are employed in such a test apparatus, it has a strong impact on the cost of the test apparatus.